Presently, developments in semiconductor integrated circuit technology are proceeding at an astonishing rate; for example, using the example of dynamic memory, from 4 megabits to 16 megabits are already in production, while the development of ultra-high density memories having a capacity of more than 64 megabits has been completed. In memory chips having a capacity of 64 megabits, in actuality, approximately 120 million MOS transistors are integrated on a silicon chip of at most 1 cm.sup.2. The present astonishing progress in LSI technology has been achieved as a result of progress in microstructurization of elements and in microfabrication technology. Accordingly, semiconductor memories, the capacity of which can be expanded simply by the accumulation on a single chip of a great number of memory cells having identical structures, have been attained at a truly astonishing rate of progress.
However, the record progress attained with regard to memory has been unattainable in the case of logical LSI. It is true that high function CPUs from 16 to 32 bit and 64 bit and various types of high function logical LSI have been developed; however, on the threshold of the ultra LSI era, great problems are being confronted in the design and production of logical LSI.
The first problem is that of how to design such chips. Logical LSI chips are configured logically to construct logic with binary signals having a value of 1 or 0 by means of the combination of the MOS transistors which function as switching elements. In this method, because a large number of transistors must be connected to one another in order to configure simple logical functions, there are problems in that:
[1] There is a limit to the increase in the degree of integration. PA1 [2] The layout pattern is complicated, PA1 [3] The number of interconnections increases, and the like. In order to solve the problem of [1] above, it is necessary to be creative in layout and minimize, as much as possible, wasted surface area.
The design of conventional 8 bit microprocessors and the like was diligently conducted by trained personnel; however, with the increase in scale of logical circuits and the increase in the number of elements, the manual design of such logical circuits requires astronomical amounts of time, that it has become, in practice, impossible. In the case of memory LSI, the possibility of layout design by means simply of the repetitive arrangement in a plane of a great number of patterns of sense amplifiers or memory cells having identical structures as is a point which essentially differs from the case of logical LSI. There has been much research and development in the so-called CAD (Computer Aided Design) field, in which computers are used in the circuitry and layout design of logical LSI; however, the present state of such efforts is such that the degree of integration attainable thereby is greatly inferior to the degree of integration obtainable manually. The CAD is presently in wide use to arrange basic gates, such as AND (logical product), OR (logical sum), or XOR (exclusive logical sum) gates, or flip flops or the like as building blocks on a chip, and connecting these building blocks to one another.
It is certain that the amount of time required for design is shortened; however, an increase in the degree of integration cannot be expected. Furthermore, as a huge number of interconnects connecting element to element run vertically and horizontally, the situation becomes such that the delay in signal propagation in the interconnection determines the operational speed of the logical LSI, and the effort to increase the speed is presented with a number of difficulties. The introduction of multivalued logical circuits is effective in solving the problems presented by the increase in interconnection. This means, in other words, the introduction of circuits having not merely the two possible values of "1" or "0", but rather, for example, the four values 0, 1, 2, or 3. It has been discovered that by means of this, it is possible to greatly reduce the number of interconnects in logical LSI.
However, the construction of such multivalued logical circuits by means of the present technology is beset by a number of difficulties; for example, more complex circuitry is necessary, and furthermore, the manufacturing production processes are complex, and the like, so that the practical application thereof is not realizable in the immediate future.
The problems present in the current logical LSI technology will be explained more clearly hereinbelow by the use of an example.
FIGS. 35(a) and 35(b) depict logical circuits which perform, with respect to three binary inputs A, B, and C, the following calculations: EQU Y.sub.1 =(A+B+C).multidot.(A+B+C)
and EQU Y.sub.2 =A.multidot.B.multidot.C+A.multidot.B.multidot.C
In the diagrams, reference numerals 3501 and 3502 indicate NOR circuits having, respectively, 3 inputs and 2 inputs, while reference numeral 3503 indicates an inverter. Furthermore, reference numerals 3504 and 3505 indicate NAND circuits, having, respectively, 3 inputs and 2 inputs. If the inverter, the 3 input NOR circuit and the 3 input NAND circuit are constructed utilizing, for example, CMOS technology, the the structure thereof are as shown in FIGS. 35(c), 35(d), and 35(e). The reference N and P in these diagrams indicate an NMOS transistor 3506 and a PMOS transistor 3507.
As is clear from FIGS. 35(a) and 35(b), complicated circuitry is required in order to express a simple logical function. The number of MOS transistors required for these circuits is 22, both in the case of the circuit Y.sub.1 and the circuit Y.sub.2. The circuit shown in FIG. 36 is a circuit which calculates Y.sub.2 ; the structure thereof is different from that of FIG. 35(b). The AND and NOR functions are expressed by means of a single CMOS gate 3601, and this somewhat simplified structure reduces the number of transistors necessary to 20. In the realization of a circuit for the calculation of Y.sub.1 by means of a similar type of structure, the final stage inverter 3402 may be omitted, so that the necessary number of transistors is further reduced to 18. However, the circuit structure is complicated, and the transistors are connected to one another in such a manner that a number of signal interconnects cross, so that it is clear that a number of problems are caused in the course of pattern layout.
Next, a multivalued logical circuit will be discussed.
FIG. 37 (a) shows an example of the characteristics of a binary multiple threshold logical element which performs important functions in multivalued logic, while FIG. 37(b) shows an example of circuitry which realizes such an element. A binary multiple threshold logical element is an element which, as shown in FIG. 37(a), outputs an output voltage of either 0 (OV) or 1 (V.sub.DD) with respect to an inputted voltage x which varies within a range of from OV to V.sub.DD (for example, 5V). In the diagram, references a, b, c, and d indicate input voltages at which the characteristics change from 1 to 0 or from 0 to 1; these have the respective values of (1/5) V.sub.DD, (2/5) V.sub.DD, (4/5) V.sub.DD, and (9/10) V.sub.DD. The circuitry shown in FIG. 37(b) is used to realize such characteristics.
For the purpose of simplicity, the circuit in FIG. 37(b) is shown as a circuit incorporating NMOS transistors (3701, 3702, 3703, and 3704) and resistor 3705. In place of resistor 3705, it is also possible to use a circuit having an E/D structure utilizing a depression mode MOS transistor as a load element. In the diagram, what is indicated by the formulas V.sub.TH =a, V.sub.TH =b, and the like, is the respective threshold values of the driver transistors constructing the inverters. In this case, the inversion voltage of the inverter (the input voltage at which 0 and 1 are inverted) is approximately identical to this threshold value. The operation of the circuit may be easily understood. When conditions are such that 0&lt;X&lt;a, then inverters 3706, 3707, and 3708 are all in an OFF state, and V.sub.DD is outputted. Accordingly, transistors 3701 and 3704 are in an ON state, and transistors 3702 and 3703 are in an OFF state, so that y is at a high level and is equal to V.sub.DD. When conditions change such that a&lt;x&lt;b, transistor 3703 changes to an ON state, so that y becomes equal to 0. When conditions are such that b&lt;x&lt;c, transistor 3704 is in an OFF state, so that y again becomes equal to V.sub.DD. When conditions are such that c&lt;x&lt;d, transistor 3702 is in an ON state, so that the output becomes equal to 0; however, when d&lt;x, transistor 3701 is an OFF state, and y again becomes equal to V.sub.DD.
In order to construct the circuit, a total of 13 transistors are necessary; 8 NMOS driver transistors, and 5 load transistors (in the case where an E/D structure is adopted). However, when a E/R structure or a E/D structure is employed, in the case where the inverter is in an ON state, a direct current is caused to flow, and power dissipation is greatly increased, so that such a structure is disadvantageous for ultralarge-scale integration. If the circuit shown in FIG. 37(b) is constructed using CMOS transistors, in order to reduce the power dissipation, the number of PMOS transistors on the load side is increased, and a total of 16 transistors (8 NMOS transistors and 8 PMOS transistors) becomes necessary.
The need to use a large number of transistors represents a disadvantage when the attainment of large scale integration is desired. However, a larger problem lies in the fact that a large number of transistors having different threshold values are needed. For example, in the example shown in the Figure, at least four types of threshold values a, b, c, and d, are necessary. Normally, the adjustment of threshold values is accomplished by using an ion implantation method, introducing impurity ions into the channel region, and varying the concentration thereof; thus, at least four ion implantations are required for threshold value adjustment.
Furthermore, in an CMOS inverter, the inversion voltage of this inverter is determined as a function of the threshold values of both the NMOS transistor and the PMOS transistor, so that it is also necessary to adjust the threshold value of the PMOS transistor. That is to say, it is necessary to precisely control 8 threshold values by means of at least 8 ion implantations. If the threshold value of any one of these transistors deviates from the designed value, the circuit will not be able to operate normally, so that the production process margin is extremely small. In addition to the fact that the production process is extremely long, it also requires an extremely high degree of control, so that little progress has been made in the practical application of multivalued logical circuits.
Furthermore, in order to exchange data between a multivalued logical circuit and a binary logic digital logic circuit which is connected thereto, multivalue-to-binary conversion between binary and multivalued values is necessary. In particular, a A/D converter is necessary for the conversion of multivalued signals to binary signals; however, this necessitates a number of elements, which presents extreme difficulties in the case where high integration is to be attained.
For example, FIG. 38 shows an example of a parallel type high speed A/D converter circuit; this circuit converts an analog signal V.sub.a to a binary signal having the 3 bits A.sub.2, A.sub.1, and A.sub.0. An explanation of the detailed operation of this circuit is omitted here; however, the circuit comprises 7 comparators, 7 registors, and a combined logical circuit, and does not merely require an extremely large number of elements, but also possesses a very large number of interconnects. It is extremely difficult to attain large scale integration of this type of circuit.
As explained above, in order to realize even simple logical functions with logical circuits employing conventional technology, a large number of elements are necessary, and the degree of integration does not increase. Furthermore, because there is no effective process for the simple design and layout of a complicated logical circuit, a large amount of time is necessary for the design of a large scale logical circuit. CAD, which utilizes a computer, employs a building block method, so that the complicated interconnection limits the increase in the degree of integration and the operation speed. With respect to multivalued logical LSI, which has attracted attention as a method which is extremely effective in the reduction of the number of interconnects, to the extent that conventional element technology or circuit technology is employed, the cicuitry is complicated, and the manufacturing process is extremely burdensome, so that in the present state of affairs, practical application presents extreme difficulties.
In addition to this, the present state of affairs is such that the advent of logical LSI having a completely new architecture which differs from conventional logical circuit structure has been greatly desired. The reason for this is that the hardware of current LSI cannot be altered once it has been produced, and a variety of calculations are executed by means of alterations in data or programs which are applied to the circuit. On the brink of the ultra-LSI age, a new breakthrough capable of solving these various problems has been strongly desired.
The present invention was designed in order to solve the problems described above; it provides a semiconductor device which realizes a circuit possessing functions identical to those of conventional circuits by the use of an extremely small number of elements, and which permits simple design and layout of complicated logical functions.